A novel low-power A2 adder scheme based on reduced transistor count Full-Adder cells
نویسندگان
چکیده
A power-efficient 8-bits digital adder using the new arithmetic A2 redundant binary representation is presented. This structure is very suitable for implementation in VLSI of mixed-signal circuits built around Multiplier Digital to Analog Converter (MDAC) cells. Using a reduced transistor count Full-Adder cells shows that our approach significantly reduces the power consumption of such adders compared to the classical scheme using classical Full-Adder cells. The adder being studied was optimized for power efficiency at 0.18μm CMOS process.
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